DPO/MSO70000 Series Option PCE3 Datasheet

DPO/MSO70000 Option PCE3 Datasheet

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The Tektronix Option PCE3 application provides the most comprehensive solution for PCI Express Gen1/2/3 Transmitter compliance testing as well as debug and validation of PCI Express devices against the specifications.

Features and benefits
  • PCIe test support. Supports compliance and validation of PCIe Gen1/2/3 interfaces based on PCIe Base and CEM specifications for Tektronix DPO/MSO70000 Series oscilloscopes
  • Automated setup. Automatically set up the oscilloscope horizontal and vertical scales to optimize signal quality for accurate analysis
  • Automated acquisition / waveform management. Automatically acquire and save the waveform as per the PCI-SIG-recommended naming convention to help manage the numerous waveforms that need to be acquired per lane for completing the Transmitter (Tx) test
  • Automated DUT control. Automatically control the DUT and step it through the various supported speeds and presets necessary for Tx testing
  • De-embedding. De-embed the effects of the channel, test fixtures and cables to provide results that more accurately represent the signal (requires Option SDLA64 Serial Data Link Analysis)
  • Test selection. Select the specification against which to perform the analysis, as well as select individual tests or groups of tests to perform targeted compliance analysis for failing tests
  • SigTest integration. User-selectable choice of the SigTest DLL or SigTest EXE (using command line interface) to perform the analysis of the acquired waveforms, providing the ability to test a system using the PCI-SIG-recommended analysis tool
  • Reporting. Compile all the results of a test run into a customizable report with Pass/Fail results for easy analysis and record keeping
  • Pattern matching. Verifies that the correct set of compliance patterns are sent by the transmitter before acquiring signals for compliance analysis
  • PHY level protocol decode. Decode and display of PCIe data in a protocol-aware view. A time-correlated event table view with waveforms allows for quickly searching through events of interest
  • Multi-lane testing. Perform analysis on multiple lanes of PCI express data to speed up the Tx analysis in a multi-lane system
  • Compliance and debug. Provides a toolkit of DPOJET-based setups to quickly switch into debug and validation mode in case a DUT fails compliance
  • Analysis and debug tools. Tektronix provides a broad range of compliance, debug, and validation tools for Transmitter (Tx), Receiver (Rx), and protocol testing
  • Comprehensive programmatic interface. Enables automation programs and scripts to call PCIe functions

Applications

Tektronix provides the most comprehensive solutions to serve the needs of engineers designing PCI Express silicon for computer systems, add-in cards, and embedded systems, as well as those validating the physical-layer compliance of PCI Express devices to the PCI Express Compliance Test Specification.

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Tektronix Option PCE3 TekExpress PCIe test selection for compliance test analysis


 

The Tektronix Option PCE3 includes Gen1/2/3 Compliance and Debug Testing and Electrical Validation for the following:

  • Root Complex
  • Endpoints
  • Switches
  • Bridges
  • Add-In cards
  • System boards
  • Embedded systems
  • Express module

 

The Tektronix Option PCE3 TekExpress application provides the most comprehensive solution for PCI Express Gen1/2/3 Transmitter compliance testing as well as debug and validation of PCI Express devices against the specifications. The Tektronix Option PCE3 application includes a TekExpress™ compliance automation solution that integrates SigTest from the PCI-SIG as well as Tektronix DPOJET-based PCI Express Jitter and Eye Diagram analysis tools for debug purposes all in a single software package.

The Tektronix Option PCE3 application is compatible with Tektronix DPO/MSO70000 series oscilloscopes that are designed to meet the challenges of the next generation of serial data standards such as PCI Express. These oscilloscopes provide the industry's leading vertical noise performance with the highest number of effective bits (ENOB) and flattest frequency response for oscilloscopes in their class. The Tektronix DPO/MSO70000 series of oscilloscopes have been approved by PCI-SIG for compliance testing.

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Tektronix Option PCE3 oscilloscope acquisition setup


 

Compliance testing

The PCI-SIG provides PCI Express compliance tests for testing PCI Express systems and add-in cards. For a PCI Express system or a device to be placed on the Integrators List, the system or device must pass interoperability and compliance testing. For electrical validation, the PCI-SIG uses SigTest Post Capture Analysis Software that uses acquisitions from an oscilloscope connected to the PCI-SIG's CBB3 (main board + riser) test fixture for add-in cards or CLB3 test fixture for systems to perform the analysis. Manually capturing the required waveforms and analyzing them is tedious, time consuming, and error prone.

The Tektronix Option PCE3 TekExpress Automation for PCI Express Transmitter Compliance greatly reduces the effort and accelerates the compliance testing for PCI Express systems and devices with several unique and innovative capabilities.

The Option PCE3 TekExpress Automation software can control the Device Under Test (DUT) using selected models of a Tektronix AFG or AWG pattern source and automatically cycle it through the various speeds, de-emphasis and presets that are necessary for the compliance test. This eliminates the error-prone manual push button approach that is normally used for DUT control on the CBB3 and CLB3 test fixtures.

A complete test run requires tens of waveforms to be acquired at different DUT settings per lane. This waveform set will increase by the number of lanes that need to be analyzed. The ability to manage and store the required data for analysis and future reference is an important criterion for any compliance solution. The Option PCE3 TekExpress automation software, apart from adjusting the horizontal and vertical settings as well as the acquisition depth for optimal signal quality for accurate analysis, also makes managing the multiple waveforms acquired for analysis easy.


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Tektronix Option PCE3 TekExpress Setup Configuration


 


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Tektronix Option PCE3 TekExpress setup preferences


Choose between SigTest EXE or SigTest DLL to analyze the acquired waveforms. This make results of the analysis consistent with the SigTest post-capture analysis software that is used at PCI-SIG workshops for compliance testing. The SigTest DLL is integrated into the solution and is used to analyze the acquired waveforms. This make results of the analysis consistent with the SigTest post capture analysis software that is used at PCI-SIG workshops for compliance testing.

The Option PCE3 TekExpress automation software provides flexibility in selecting the data rates, voltage swing, presets and the tests to run, and also provides the option to de-embed the effects of the channel and the test fixtures and provide an accurate representation of the signal at the pins as required by the specification.

All the analysis results are compiled in an PDF/HTML-format report that can include pass/fail summary, eye diagrams, setup configuration, and user comments. The contents of the report can be customized to include information of interest such as append results and custom report generation based on test name/pass fail/equalization.


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Tektronix Option PCE3 TekExpress report generation preferences



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Tektronix Option PCE3 TekExpress results summary


Debug and validation

If a DUT or Add-In card fails any portion of the compliance test, the application includes a DPOJET-based debug and analysis toolkit that is customized for debug and validation of PCI Express interfaces.

The new jitter measurements introduced with PCIe Gen3 provide separate limits for data dependent (DDJ) and uncorrelated deterministic jitter (UDJDD). It is important to separate DDJ (which can be compensated with transmitter and receiver equalization) and UDJDD (which can be caused by effects such as crosstalk and power supply noise).

Apart from the above Jitter measurements Pulse Width Jitter (PWJ) is a new measurement that addresses the increased channel loss at 8 Gb/s. The purpose of the PWJ measurement is to ensure that lone bits meet minimum pulse width requirements. All new jitter measurements implement Q-scale extrapolation as defined in the base specification. PCE3 provides the complete set of PCI Express 3.0 jitter measurements enabling silicon designers to verify that their silicon meets the base specification requirements.

Furthermore, the base specification requirements are defined at the pins of the transmitter. Before the measurements are computed the test channel must be de-embedded. De-embed filters can be easily created using the Tektronix Option SDLA64 Serial Data Link Analysis software and then quickly entered into the PCE3 base specification measurement setup and saved for future use. In addition to jitter, Option PCE3 also provides voltage, package loss, and transmitter equalization measurements.

Option PCE3 leverages the channel modeling and receiver equalization functionality of the Tektronix Option SDLA64 software to support CEM measurements. Unlike other solutions, Opt. PCE3 provides full visibility to the signal as it has been modified to embed the compliance channel and provide receiver equalization. Eye diagrams and measurements can be set up to visually see the results of channel embedding, CTLE application, and DFE. For example when determining the optimal Rx Equalization settings (CTLE setting and DFE tap value) the resulting eye diagrams and measurements show the effects of post processing on the acquired signal. Compliance measurements can then be taken on the waveform.


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Tektronix Option PCE3 TekExpress PCI Express test report



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DPOJet PCE3 base specification measurement suite



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DPOJet PCE3 base specification measurement suite


Comprehensive programmatic interface

The programmatic interface seamlessly integrates the Option PCE3 TekExpress test automation application with a high-level automation layer such as Visual Basic, MicrosoftNet, C#, C++, Python, or a Web application. This lets you control the state of the TekExpress application running on a local or a remote computer.

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Programming examples are found in the application examples folder.


 

PCI Express serial triggering and Analysis (Option SR-PCIe)

Decode and Display of PCIe data in a protocol-aware view with the characters and names that are familiar from the standard such as the ordered sets: SKP, Electrical Idle, and EIEOS. A time correlated event table view with waveform allows for quickly searching through events of interest simultaneously. The PCIe trigger is easily configured through Bus Setup under the oscilloscope's Vertical menu with a variety of user-adjustable settings. The PCIe data stream is integrated with serial bus trigger and search for PCIe gen 1 and 2 allows for triggering on information of interest.


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PCIe Gen3 compliance pattern Preset P8 (-3.5dB de-emphasis with +3.5dB preshoot) decoded in waveform view as "87h" or Results Table as either "87h" or "1000b" per Section 4.2.3.2 Encoding of Presets, from PCI Express Base Specification, Rev 3.1.


 


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Comprehensive measurements for PCIe validation, debug, and precompliance

Tektronix Option PCE3 provides measurements that span multiple test points and versions of the PCIe specification. All PCIe specifications, test points, and measurements supported are listed in the following sections.

Test methodSpec revisionPCI Express specification titleTest points defined
Rev 1.1 Rev 1.1 Base SpecificationTransmitter and Receiver
Rev 1.1 CEM SpecificationSystem and Add-in Card Reference Clock
Rev 1.0 Express Module SpecificationTransmitter Path and System Board
Rev 1.0 PCMCIA Express Card StandardHost System Transmitter
Express Card Transmitter
Ver. 3.0 Rev 1.1 Mobile PCI Express Module (MXM) Electromechanical SpecificationPCI Express
Rev 2.0 Rev 1.0 External Cabling SpecificationTransmitter and Receiver Path
Rev 2.0 Base SpecificationTransmitter and Receiver
Mobile Low-power Transmitter
Rev 2.0 CEM SpecificationSystem and Add-in Card (3.5 and 6 dB de-emphasis)
Ver. 3.0 Rev 1.1 Mobile PCI Express Module (MXM) Electromechanical SpecificationPCI Express
Rev 3.0 Rev 1.0 Base SpecificationTransmitter
Rev 1.0 CEM SpecificationSystem and Add-in Card
Rev 3.0 Test SpecificationSystem and Add-in Card

Test setup connection diagrams


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Automatic DUT control for x1 or x16 DUTs (platforms) connection diagram



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Automatic and manual DUT control for x1, x4, x8, or x16 DUTs (add-in cards) connection diagram



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Manual DUT control for x1 or x16 DUTs (platforms) connection diagram



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Automatic DUT control for x4 or x8 DUTs (platforms) connection diagram



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Manual DUT control for x4 or x8 DUTs (platforms) connection diagram

Specifications

All specifications apply to all models unless noted otherwise.

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Supported base specification measurements
Differential 8 GT/s transmitter (Tx) output measurements
ParameterSymbol
Tx Voltage with No Tx EqualizationVTX-NO-EQ
Minimum Swing during EIEOSVTX-EIEOS
Pseudo Package Lossps21TX
Data-dependent JitterTTX-DDJ
Tx Uncorrelated Deterministic JitterTTX-UDJDD
Tx Uncorrelated Total JitterTTX-UTJ
Deterministic DjDD Uncorrelated Pulse Width JitterTTX-UPW-DJDD
Total Uncorrelated Pulse Width JitterTTX-UPW-TJ
Differential transmitter (Tx) output measurements
ParameterSymbol(s)2.5 GT/s Rev 1.1/2.0 5 GT/s Rev 2.0 
Clock RecoveryNASpecifiedSpecified
Unit IntervalUISpecifiedSpecified
Differential Peak-to-Peak Tx Voltage SwingVTX-DIFF-P-P
VTX-SWING
VTX-EYE-FULL
SpecifiedSpecified
Low-power Differential Peak-to-Peak Tx Voltage SwingVTX-SWING-LOW
VTX-EYE-HALF
SpecifiedSpecified
De-emphasized Output Voltage RatioVTX-DE-RATIONot SpecifiedSpecified
Instantaneous Lane Pulse WidthTMIN-PULSENot SpecifiedSpecified
Transmitter Eye including All Jitter SourcesTTX-EYE
TTX-EYE-TJ
SpecifiedSpecified
Maximum Time between the Jitter Median and Maximum Deviation from the MedianTTX-EYEMEDIAN-to-MAXJITTERSpecifiedSpecified
Deterministic JitterTTX-DJ-DDNot SpecifiedSpecified
Tx RMS Jitter <1.5 MHzTTX-LF-RMSNot SpecifiedSpecified
D+/D– Tx Output Rise/Fall TimeTTX-RISE
TTX-FALL
SpecifiedSpecified
Tx Rise/Fall MismatchTRF-MISMATCHNot SpecifiedSpecified
AC Peak-to-Peak Common Mode Output VoltageVTX-CM-AC-PPNot SpecifiedSpecified
AC Peak Common Mode Output VoltageVTX-CM-AC-PSpecifiedSpecified
Absolute Delta of DC Common Mode Voltage between D+ and D–VTX-CM-DC-LINE-DELTASpecifiedSpecified
Differential receiver (Rx) input measurements 1
ParameterSymbols2.5 GT/s Rev 1.1/2.0 5 GT/s Rev 2.0 
Clock RecoveryNASpecifiedNot Specified
Unit IntervalUISpecifiedSpecified
Minimum Receiver Eye OpeningVRX_EYESpecifiedSpecified
Receiver Deterministic Jitter – DJTRX_DJ_DDNot SpecifiedSpecified
Minimum Width Pulse at RxTRX-MIN-PULSENot SpecifiedSpecified
Maximum Time between the Jitter Median and Maximum Deviation from the MedianTTX-EYEMEDIAN-to-MAXJITTERSpecifiedNot Specified
Rx AC Common Mode VoltageVRX-CM-AC-PSpecifiedSpecified

1 The Rx input measurements are not specified for 8 GT/s.

Supported CEM specification measurements
Add-in Card 8 GT/s transmitter path compliance measurements
ParameterSymbol
Transition Eye VoltagePCIe V-TXA
Nontransition Eye VoltagePCIe V-TXA-d
Eye WidthPCIe T-TXA
Add-in Card transmitter path compliance measurements
ParameterSymbol(s)2.5 Gt/s Rev 1.1/2.0 5 GT/s Rev 2.0 
Clock RecoveryNASpecifiedSpecified
Unit IntervalUISpecifiedSpecified
Eye Height of Transition BitsVTXASpecifiedSpecified
Eye Height of Nontransition BitsVTXA_dSpecifiedSpecified
Eye Width with Sample Size of 106 UITTXA in Rev 1.1 SpecifiedNot Specified
Jitter Eye Opening at BER 10–12TTXA in Rev 2.0 SpecifiedSpecified
Maximum Median-Max Jitter Outlier with Sample Size of 106 UIJTXA-MEDIAN-to-MAX-JITTERSpecifiedNot Specified
Total Jitter at BER 10–12TJ at BER 10–12Not SpecifiedSpecified
Deterministic Jitter at BER 10–12Max DJNot SpecifiedSpecified
System board transmitter path measurements
ParameterSymbol(s)2.5 GT/s Rev 1.1/2.0 5 GT/s Rev 2.0 
Clock RecoveryNASpecifiedSpecified
Unit IntervalUISpecifiedSpecified
Eye Height of Transition BitsVTXSSpecifiedSpecified
Eye Height of Nontransition BitsVTXS_dSpecifiedSpecified
Eye Width with Sample Size of 106 UITTXS in Rev 1.1 SpecifiedNot Specified
Jitter Eye Opening at BER 10–12TTXS in Rev 2.0 SpecifiedSpecified
Maximum Median-Max Jitter Outlier with Sample Size of 106 UIJTXA-MEDIAN-to-MAX-JITTERSpecifiedNot Specified
Total Jitter at BER 10–12TJ at BER 10–12Not SpecifiedSpecified
Deterministic Jitter at BER 10–12Max DJNot SpecifiedSpecified
Reference clock measurements
ParameterSymbol2.5 Gt/s Rev 1.1/2.0 
Reference Clock Phase Jitter at BER 10–6NASpecified
PCI ExpressModule™ measurements
ExpressModule Add-in Card transmitter path measurements
ParameterSymbolRev 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVTXASpecified
Eye Height of Nontransition BitsVTXA_dSpecified
Eye Width with Sample Size of 106 UITTXAin Rev 1.1 Specified
Jitter Eye Opening at BER 10–12NASpecified
Maximum Median-Max Jitter Outlier with Sample Size of 106 UIJTXA-MEDIAN-to-MAX-JITTERSpecified
ExpressModule system board transmitter path measurements
ParameterSymbolGen1 Rev 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVTXSSpecified
Eye Height of Nontransition BitsVTXS_dSpecified
Eye Width with Sample Size of 106 UITTXSSpecified
Jitter Eye Opening at BER 10–12NASpecified
Maximum Median-Max Jitter Outlier with Sample Size of 106 UIJTXA-MEDIAN-to-MAX-JITTERSpecified
PCI Express external cabling measurements
External cabling transmitter path measurements
ParameterSymbolRev 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVTXASpecified
Eye Height of Nontransition BitsVTXA_dSpecified
Jitter Eye Opening at BER 10–12TrxA at BER 10–12Specified
Eye Width with Sample Size of 106 UITrxA at 106 SamplesSpecified
External cabling receiver path measurements
ParameterSymbolGen1 Rev 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVRXASpecified
Eye Height of Nontransition BitsVRXA_dSpecified
Jitter Eye Opening at BER 10–12TrxA at BER 10–12Specified
Eye Width with Sample Size of 106 UITrxA at 106 SamplesSpecified
PCMCIA ExpressCard™ measurements
ExpressCard - Module transmitter path measurements
ParameterSymbolRelease 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVTXASpecified
Eye Height of Nontransition BitsVTXA_dSpecified
Eye Width across any 250 UIsTTXASpecified
ExpressCard™ - Host system transmitter path measurements
ParameterSymbolRelease 1.0 
Clock RecoveryNASpecified
Unit IntervalUISpecified
Eye Height of Transition BitsVtxSSpecified
Eye Height of Nontransition BitsVtxS_dSpecified
Eye Width across any 250 UIsTTxSSpecified
MXM measurements
PCI Express measurements 1
ParameterSymbolRelease 1.1 
Eye Height of Transition BitsVTXSSpecified
Eye Height of Nontransition BitsVTXS_dSpecified
Width at BERTTXSSpecified
Deterministic JitterDJSpecified
Total JitterTJSpecified

1 All de-emphasis levels supported

Ordering information

PCE3 1
PCI Express 3.0/2.0/1.x Physical-layer Test Application for DPO/MSO70K Series oscilloscopes
New instrument orders
Option PCE3
Product upgrades
Option DPO-UP PCE3
Floating licenses
Option DPO-UP PCE3

1 Requires Option DJA (DPOJET Jitter and Eye Diagram Analysis) and Option SDLA64 (Serial Data Link Analysis Visualizer). Option DJA is standard on MSO70000 Series oscilloscopes, and can be ordered for DPO70000 Series oscilloscopes.

Recommended DPO/MSO70000 Series Oscilloscopes
2.5 Gb/s (PCI Express 1.0/1.1)
DPO/MSO70000 Series (6 GHz or higher bandwidth models required for compliance testing. 4 GHz bandwidth models can be used for debug only.)
5.0 Gb/s (PCI Express 2.0)
DPO/MSO70000 Series (12.5 GHz or higher bandwidth models)
8.0 Gb/s (PCI Express 3.0)
DPO/MSO70000 Series (16 GHz or higher bandwidth models, minimum of 12.5 GHz is recommended)
Accessories
Recommended accessories
P7500 and P7600 Series
TriMode™ Differential Probe
Option SDLA64
Serial Data Link Analysis Visualizer
Recommended for automated DUT control
Tektronix AFG3252
Arbitrary Function Generator
Tektronix AFG3252C
Arbitrary Function Generator
AWG5002B/C
Arbitrary Waveform Generator
AWG5012B/C
Arbitrary Waveform Generator
AWG5014B/C
Arbitrary Waveform Generator
AWG7082B/C
Arbitrary Waveform Generator
AWG7122B/C
Arbitrary Function Generator
AWG70001A
Arbitrary Waveform Generator
AWG70002A
Arbitrary Waveform Generator
Recommended test fixtures, cables, and tools
DescriptionImage
Description: PCI Express Compliance Base Board (CBB) test fixture, revision 3.0. For testing PCI Express Add-in Cards, x1/x4/x8/x16. Vendor: PCI-SIG
www.pcisig.com/specifications/order_form
Vendor PN: CBB3
Tektronix PN: Only available from PCI-SIG
Quantity: 1 
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Description: PCI Express Compliance Load Board (CLB3) test fixture, revision 3.0. For testing PCI Express Platforms, x1 & x16 PCIe connectors. Vendor: PCI-SIG
www.pcisig.com/specifications/order_form
Vendor PN: x1/x16 CLB3
Tektronix PN: Only available from PCI-SIG
Quantity: 1 
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Description: PCI Express Compliance Load Board (CLB3), Revision 3.0. For testing PCI Express Platforms, x4 & x8 PCIe connectors. Vendor: PCI-SIG
www.pcisig.com/specifications/order_form
Vendor PN: x4/x8 CLB3
Tektronix PN: Only available from PCI-SIG
Quantity: 1 
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Description: Any ATX PC power supply Vendor: Tektronix recommends "PC Power & Cooling 750W Silencer MK III Series" or similar.
Quantity: 1 

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Description: SMP terminator, 50 Ω, limited detent. Vendor: Fairview Microwave
www.fairviewmicrowave.com/rf-load-0.25-watts-26.5-ghz-smp-female-st2645-p.aspx
Vendor PN: ST2645
Tektronix PN: 131-9399-xx
Quantity needed per PCIe DUT link width:
  • x1: 0 
  • x4: 6 
  • x8: 14 
  • x16: 30 
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Description: SMA Female to BNC Male adapter. Vendor: Tektronix
Tektronix PN: 015-0572-xx
www.tektronix.com
Quantity: 2 
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Description: DC Block, SMA, 26 GHz Vendor: Tektronix
www.tektronix.com
Tektronix PN: PSPL5500A, PSPL5501A, or PSPL5508
Quantity: 2 
Note: This is an optional accessory and not shown in any of connection diagrams, but can be used if DC offset is encountered in any signal path.
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Description: USB2.0 Cable, Type A Male to Type B Male, 6 foot Vendor: Tektronix
Tektronix PN: 174-6053-xx
www.tektronix.com
Quantity: 1 

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Description: SMA-to-SMA, H+S SF104E Phase Kit (#84077556), Straight, 1m, 1.5 ps phase-matched. Vendor: Tektronix
www.tektronix.com
Tektronix PN: PMCABLE1M
Quantity: 1 cable pair per lane

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Description: SMA-to-SMP right-angle cable pair, 102 mm, 1 ps phase-matched. Vendor: Rosenberger
www.rosenberger.com/us_en
Vendor PN: 71L-19K2-32K1-00102D
Tektronix PN: 174-6657-xx
Quantity: 1 cable pair
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Description: SMA-to-SMP right-angle cable pair, 1 m, 1 ps phase-matched (one for AFG to Rx Lane0, one for 100 MHz RefClk for Ch3+4 for System Testing) Vendor: Rosenberger
www.rosenberger.com/us_en
Vendor PN: 71M-19K2-32S1-01000D
Tektronix PN: 174-6659-xx
Quantity: 1 cable pair
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Description: SMP to SMP right-angle cable pair, 305 mm, 2.5 ps phase-matched set. Vendor: Rosenberger
www.rosenberger.com/us_en
Vendor PN: 71L-19K2-19K2-00305C
Tektronix PN: 174-6658-xx
Quantity: 1 cable pair
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Description: SMA torque wrench, 8.0 in-lbs. Vendor: Fairview Microwave
www.fairviewmicrowave.com/sma-fixed-torque-wrench-click-st-sma3-p.aspx
Vendor PN: ST-SMA3
Tektronix PN: 003-1940-xx
Quantity: 1 
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Description: SMP right-angle cable extraction tool. Vendor: Fairview Microwave
www.fairviewmicrowave.com/undefined-mmtl2682-p.aspx
Vendor PN: MMTL2682
Tektronix PN: 003-1941-xx
Quantity: 1 
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Description: SMP terminator installation/extraction tool. Vendor: Fairview Microwave
www.fairviewmicrowave.com/undefined-mmtl4991-p.aspx
Vendor PN: MMTL4991
Tektronix PN: 003-1939-xx
Quantity: 1 
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Additional information
PCI Express 3.0 reciever testing

A complete PCI Express 3.0 Receiver testing solution from Tektronix. Includes stressed pattern generation as required by PCI-SIG test specifications and support for automated clock multiplication and eye opening measurements. Automated DUT loopback control simplifies the testing process and reduces time to test results. The receiver testing solution also supports adding pre-emphasis to the stress pattern, common-mode interference testing, and PLL loop BW testing.

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PCIe receiver test setup


 

The Receiver testing solution consists of the following components:

  • BERTScope C Model for Pattern Generation, stressed eye sources, and Error Detection
  • New DPP125C Option ECM that provides Eye opener, Clock doubler and clock Multiplier functionality
  • New BSAITS125 that provides CM/DM interference and compliant ISI channels and programmable, variable expanded ISI with Opt EXP
  • New Opt PCIE8G PLL analysis for Gen1/2/3 
  • New BSAPCI3 SW for Auto calibration, link training, and testing
  • MSO/DPO70000 Series Real-Time Oscilloscope for calibration

 

TLA7SA00 Series Protocol Analyzers

The TLA7SA00 Series logic protocol analyzer modules provide an innovative approach to PCI Express validation that spans all layers of the protocol from the physical layer to the transaction layer.

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TLA7SA00 series instrument


 

Feature rich software provides improved information density for viewing statistical summary and protocol analysis using innovative Transaction and Summary Profile windows.

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TLA7SA00 data views


 

Hardware capabilities including hardware acceleration, OpenEYE, ScopePHY, and FastSYNC provide fast access to data and helps shorten the time it takes to build confidence in the test system. Powerful trigger and filtering capabilities provide the ability to quickly focus on the data of interest. Provides a complete suite of probing solutions targeted for various form factors and applications.

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