68060 Processor Support
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- Full speed state analysis up to 50 MHz
- Disassembly shows acquired data in the processor's instruction set mnemonics.
- Symbolically identifies all processor bus cycles
- Acquired data can be linked directly to HLL source files for source level debug
- 500 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc.
- All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
Probing and Package Styles
Probe adapter designed for a socketed 206-pin PGA package.
Minimum System Requirements
- TLA7xx mainframe and one TLA7L3 acquisition module, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 64M deep available)
- Or TLA603 instrument, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 1M deep available)
- add qty 6: P6417 -or- P6418 general purpose probes (REQUIRED)
- TLA application software version 1.0 or greater
- Instrument setup software including clocking and channel assignments
- Symbol table of all bus cycle names
- Disassembler for 68060 processors
- Probe adapter for a socketed 206-pin PGA package.
- User manual
|device description||product number|
|add qty 6: P6417 -or- P6418 general purpose probes (REQUIRED)||P6417/P6418|