486 and 5x86 Microprocessor Support
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This package allows full speed state analysis for the i486 processors up to 50 MHz. Disassembly shows acquired data in the processor’s defined instruction set mnemonics. Disassembled data can be linked directly to HLL source files. This enables an engineer to track program execution at the HLL source code level rather than the assembly language level.
500 ps timing resolution enables detailed analysis of setup and hold times, edge-to-edge relationships, control timing, etc. All data acquired by the logic analyzer is time stamped to enable accurate time correlation of code execution to other system busses or hardware activity.
The probe adapter provides a physical connection to the processor and enables the engineer to monitor bus timing and code execution.
- State analysis up to 50 MHz
- Symbolically identifies all processor bus cycles
- Link acquired data directly to HLL source files for debug
- 500 ps timing resolution
- Probe adapter supports PGA-168 package style
Minimum System Requirements
- TLA7xx mainframe and one TLA7x3 acquisition module, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 64M deep available)
- Or TLA603 instrument, 102 channels, 100 MHz state, 32K deep (200 MHz state, 136 channels and up to 1M deep available)
- Standard P64xx probes
- TMS 107 software v.1.0 requires TLA application software v.1.0 or greater
- Instrument setup software including clocking and channel assignments
- Symbol table of all bus cycle names
- Disassembler for i486 processors
- User manual
|device description||product number|
|486/5x86 support (software and manual)||TMS107|
|add 486/5x86 probe adapter (REQUIRED)||TMS107 (opt 01)|